Field of the Invention
The present invention generally relates to multiprocessor computer systems and, more specifically, to a heterogeneous multiprocessor design for power-efficient and area-efficient computing.
Description of the Related Art
Battery-powered mobile computing platforms have become increasingly important in recent years, intensifying the need for efficient, low power systems that deliver highly scalable computational capacity with diminishing cost. A typical mobile device may need to operate over a wide performance range, according to workload requirements. Different performance ranges are conventionally mapped to a different operating mode, with power consumption proportionally related to performance within a given operating mode. In a low-power sleep mode, the mobile device may provide a small amount of computational capacity, such as to maintain radio contact with a cellular tower. In an active mode, the mobile device may provide low-latency response to user input, for example via a window manager. Many operations associated with typical applications execute with satisfactory performance in an active mode. In a high-performance mode, the mobile device needs to provide peak computational capacity, such as to execute a real-time game or perform transient user-interface operations. Active mode and high-performance mode typically require progressively increasing power consumption.
A number of techniques have been developed to improve both performance and power efficiency for mobile devices. Such techniques include reducing device parasitic loads by reducing device size, reducing operating and threshold voltages, trading off performance for power-efficiency, and adding different circuit configurations tuned to operate well under certain operating modes.
In one example, a mobile device processor complex comprises a low-power, but low-performance processor and a high-performance, but high-power processor. In idle and low activity active modes, the low-power processor is more power efficient at lower performance levels and is therefore selected for execution, while in high-performance modes, the high-performance processor is more power efficient and is therefore selected for execution of larger workloads. In this scenario, the trade-off space includes a cost component since the mobile device carries a cost burden of two processors, where only one processor can be active at a time. While such a processor complex enables both low power operation and high-performance operation, the processor complex makes inefficient use of expensive resources.
As the foregoing illustrates, what is needed in the art is a more efficient technique for accommodating a wide range of different workloads.